This application claims priority from French App""n 93-07728, filed Jun. 21, 1993, which is hereby incorporated by reference.
The invention relates to electronic systems formed by a plurality of units communicating with one another by means of bus-type links.
A standard type of bus is usually constituted by several specialized lines. Some of these lines are used to convey signals, called functional signals, such as control, address and data signals as well as clock signals in the case of synchronous systems. Other lines of the bus are assigned to the electrical power supply of the circuits that form the units of the system, and these lines are connected to a generator of power supply voltages. Thus, a bus will comprise at least two power supply lines, one of which generally defines a ground of the system, the other power supply lines being taken to potentials defined according to the needs of the technology used.
Thus, for example, the buses that conform to the I2C standard are constituted by four lines:
an xe2x80x9cSDAxe2x80x9d line for the two-way serial transmission of control, address and data signals,
an xe2x80x9cSCLxe2x80x9d line to transmit a clock signal,
a xe2x80x9cVssxe2x80x9d line assigned to the ground and
a xe2x80x9cVccxe2x80x9d line designed to receive a positive supply potential.
This I2C standard bus is used, for example, to set up systems for application in large-scale consumer electronics or in the field of automobile electronics. Such systems are typically formed by a microprocessor-based central sub-system that uses the bus to control peripheral units. A possible example of a peripheral unit would be an EEPROM type electrically erasable programmable memory that would enable data to be saved when there are no permanent power supply voltages. These memories are used particularly in automobile electronics to implement decentralized functions that call for non-volatile storage of data elements. This is the case, for example, with anti-locking systems for wheels, or with the control of xe2x80x9cair bagxe2x80x9d type safety systems or with various electrical tuning and adjusting systems (for car radios, seat adjustment etc.).
Other examples of the use of I2C buses include systems using microprocessor-based chip-card (smart card) readers.
Of course, the choice of a bus standard for a system dictates the type of interface for the units that form the system. This also has the consequence of dictating the type of connector that can be used. This connector should have a number of terminals that is at least equal to the number of lines of the bus. Similarly, the integrated circuits that are specially designed to be compatible with the chosen standard must also be provided with the same number of terminals. Now, a substantial portion of the manufacturing cost of system arises out of the cost of the connectors used, and this cost is directly related to the number of their terminals. It is therefore preferable that this number should be as small as possible. Thus, by providing for only one series link to convey the commands, the addresses and the data elements at the same time, the I2C standard enables the number of lines of the bus to be limited to four.
Another advantage of having a small number of bus lines lies in the improved reliability of the system due to the fact that reducing the number of terminals of the connectors gives rise to a proportional reduction in the risks of malfunctioning in the corresponding electrical contacts. Similarly, reducing the number of lines leads to a reduction in the cost of the wiring which may be high in the case of automobile applications for example.
Another case in which it is worthwhile to reduce the number of lines is when it is sought to release a terminal of a connector to enable access to an additional terminal of the integrated circuit, designed to be inserted into this connector. This additional terminal will be designed, for example, to connect a test line that can be used during the finalizing stage or when the system is being installed.
The invention is therefore aimed at seeking solutions that can be used to reduce the number of lines of the communication buses to the maximum extent while at the same time maintaining compatibility with an imposed standard, especially in keeping the communications protocol laid down by this standard.
To this end, an object of the invention is a system comprising a transmitter of functional signals such as data, address, control or clock signals, a power supply circuit, a plurality of units matched with a protocol and a communications bus of a first type, the bus of the first type comprising notably two power supply lines designed to convey power supply potentials delivered by the power supply circuit and at least one functional line designed to convey one of the functional signals delivered by the transmitter of functional signals, wherein the system includes at least one communications bus of a second type, defined by a modification of the bus of the first type, according to which the power supply lines are eliminated and there is added a complementary functional line supplied with a functional signal that is complementary to the functional signal and wherein at least one of the units of the system is connected to a communications bus of the second type by means of an adaptation circuit comprising a power supply regenerator to produce regenerated power supply potentials from the functional signal and the complementary functional signal.
Since, as a general rule, the high and low levels of the functional signals correspond to power supply potentials, the invention can be applied to most of the existing standard buses, without there being any need to modify the levels of the functional signal normally available at one of the lines of the bus. Thus, according to another characteristic of the invention, the system includes a conversion circuit with an inverter amplifier supplied with the power supply potentials, receiving the functional signal at input and giving the complementary functional signal at output.
According to a particular embodiment, the power supply regenerator has a full-wave rectifier circuit receiving the functional signal and the complementary functional signal at input and giving the regenerated power supply potentials at output.
Should it be necessary to have an amplification of the functional signal in terms of current or voltage, then provision could be made, according to one alternative embodiment of the invention, for the conversion circuit to comprise a non-inverter amplifier supplied with the power supply potentials, receiving the functional signal at input and giving an amplified functional signal at output, this amplified functional signal replacing the initial functional signal at the input of the rectifier circuit.
According to yet another variant of an embodiment of the invention, the power supply regenerator is provided with means to adjust the levels of the potentials that it gives. This arrangement could prove to be useful or necessary if there should be too great a difference between the levels of the power supply potentials of the amplifiers used to give the complementary functional signal and/or the amplified functional signal and the levels of the power supply potentials and/or of the functional signal that can be used by the unit.
The invention can be applied in a particularly advantageous way in a system according to the I2C standards, especially when MOS or CMOS technology is used. Since the bus of the second type used according to the invention has only three lines, it will be possible to use the connectors initially designed for the discrete three-terminal components such as transistors. It is therefore possible to use conventional packaging tools that have been developed long ago for components of this type. This will lead to a saving in manufacturing costs due to the low price of the connectors and to reduced outlay on tools.
According to other aspects of the invention, at least one unit and the associated adaptation circuit form part of one and the same integrated circuit, and this unit may be an electrically erasable programmable memory of the EEPROM type.
The invention also relates to the application of the system defined here above to make systems that use microprocessor-based card readers.
According to a disclosed class of innovative embodiments, there is provided a system comprising: a transmitter of functional signals such as data, address, control or clock signals; a power supply circuit; a plurality of units matched with a protocol; and a communications bus of a first type, comprising two power supply lines designed to convey power supply potentials delivered by the power supply circuit and at least one functional line designed to convey one of the functional signals delivered by the transmitter of functional signals, wherein the system also includes at least one communications bus of a second type, defined by a modification of the bus of the first type, according to which the power supply lines are eliminated and there is added a complementary functional line supplied with a functional signal that is complementary to the functional signal, and wherein at least one of the units of the system is connected to a communications bus of the second type by means of an adaptation circuit comprising a power supply regenerator to produce regenerated power supply potentials from the functional signal and the complementary functional signal.